235 lines
8.9 KiB
Go
235 lines
8.9 KiB
Go
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// Copyright 2017 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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// pcm means I2S.
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package bcm283x
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import (
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"errors"
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"fmt"
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"time"
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"periph.io/x/periph/conn/physic"
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)
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type pcmCS uint32
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// Pages 126-129
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const (
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// 31:26 reserved
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pcmStandby pcmCS = 1 << 25 // STBY Allow at least 4 PCM clock cycles to take effect
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pcmSync pcmCS = 1 << 24 // SYNC Two PCM clocks have occurred since last write
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pcmRXSignExtend pcmCS = 1 << 23 // RXSEX Sign extend RXZ data
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pcmRXFull pcmCS = 1 << 22 // RXF RX FIFO is full
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pcmTXEmpty pcmCS = 1 << 21 // TXE TX FIFO is empty
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pcmRXData pcmCS = 1 << 20 // RXD RX FIFO contains data
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pcmTXData pcmCS = 1 << 19 // TXD TX FIFO ready to accept data
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pcmRXR pcmCS = 1 << 18 // RXR RX FIFO needs reading
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pcmTXW pcmCS = 1 << 17 // TXW TX FIFO needs writing
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pcmRXErr pcmCS = 1 << 16 // RXERR RX FIFO error
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pcmTXErr pcmCS = 1 << 15 // TXERR TX FIFO error
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pcmRXSync pcmCS = 1 << 14 // RXSYNC RX FIFO is out of sync
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pcmTXSync pcmCS = 1 << 13 // TXSYNC TX FIFO is out of sync
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// 12:10 reserved
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pcmDMAEnable pcmCS = 1 << 9 // DMAEN Generate TX&RX DMA DREQ
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// 8:7 RXTHR controls when pcmRXR is set
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pcmRXThresholdOne pcmCS = 0 << 7 // One sample in RX FIFO
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pcmRXThreshold1 pcmCS = 1 << 7 // RX FIFO is at least (?) full
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pcmRXThreshold2 pcmCS = 2 << 7 // ?
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pcmRXThresholdFull pcmCS = 3 << 7 // RX is full
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// 6:5 TXTHR controls when pcmTXW is set
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pcmTXThresholdEmpty pcmCS = 0 << 5 // TX FIFO is empty
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pcmTXThresholdNotFull1 pcmCS = 1 << 5 // At least one sample can be put
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pcmTXThresholdNotFull2 pcmCS = 2 << 5 // At least one sample can be put
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pcmTXThresholdOne pcmCS = 3 << 5 // One sample can be put
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pcmRXClear pcmCS = 1 << 4 // RXCLR Clear RX FIFO; takes 2 PCM clock to take effect
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pcmTXClear pcmCS = 1 << 3 // TXCLR Clear TX FIFO; takes 2 PCM clock to take effect
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pcmTXEnable pcmCS = 1 << 2 // TXON Enable TX
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pcmRXEnable pcmCS = 1 << 1 // RXON Enable FX
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pcmEnable pcmCS = 1 << 0 // EN Enable the PCM
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)
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type pcmMode uint32
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// Page 129-131
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const (
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// 31:29 reserved
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pcmClockDisable pcmMode = 1 << 28 // CLK_DIS Cleanly disable the PCM clock
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pcmDecimation32 pcmMode = 1 << 27 // PDMN; 0 is factor 16, 1 is factor 32
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pcmRXPDMFilter pcmMode = 1 << 26 // PDME Enable input CIC filter on PDM input
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pcmRXMerge pcmMode = 1 << 25 // FRXP Merge both channels as single FIFO entry
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pcmTXMerge pcmMode = 1 << 24 // FTXP Merge both channels as singe FIFO entry
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pcmClockSlave pcmMode = 1 << 23 // CLKM PCM CLK is input
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pcmClockInverted pcmMode = 1 << 22 // CLKI Inverse clock signal
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pcmFSSlave pcmMode = 1 << 21 // FSM PCM FS is input
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pcmFSInverted pcmMode = 1 << 20 // FSI Invese FS signal
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pcmFrameLengthShift = 10 //
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pcmFrameLenghtMask pcmMode = 0x3F << pcmFrameLengthShift // FLEN Frame length + 1
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pcmFSLenghtMask pcmMode = 0x3F << 0 // FSLEN FS pulse clock width
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)
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type pcmRX uint32
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// Page 131-132
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const (
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pcmRX1Width pcmRX = 1 << 31 // CH1WEX Legacy
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pcmRX1Enable pcmRX = 1 << 30 // CH1EN
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pcmRX1PosShift = 20
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pcmRX1PosMask pcmRX = 0x3F << pcmRX1PosShift // CH1POS Clock delay
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pcmRX1Channel16 pcmRX = 8 << 16 // CH1WID (Arbitrary width between 8 and 16 is supported)
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pcmRX2Width pcmRX = 1 << 15 // CH2WEX Legacy
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pcmRX2Enable pcmRX = 1 << 14 // CH2EN
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pcmRX2PosShift = 4
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pcmRX2PosMask pcmRX = 0x3F << pcmRX2PosShift // CH2POS Clock delay
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pcmRX2Channel16 pcmRX = 8 << 0 // CH2WID (Arbitrary width between 8 and 16 is supported)
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)
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type pcmTX uint32
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// Page 133-134
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const (
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pcmTX1Width pcmTX = 1 << 31 // CH1WX Legacy
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pcmTX1Enable pcmTX = 1 << 30 // CH1EN Enable channel 1
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pcmTX1PosShift = 20
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pcmTX1PosMask pcmTX = 0x3F << pcmTX1PosShift // CH1POS Clock delay
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pcmTX1Channel16 pcmTX = 8 << 16 // CH1WID (Arbitrary width between 8 and 16 is supported)
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pcmTX2Width pcmTX = 1 << 15 // CH2WEX Legacy
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pcmTX2Enable pcmTX = 1 << 14 // CH2EN
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pcmTX2PosShift = 4
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pcmTX2PosMask pcmTX = 0x3F << pcmTX2PosShift // CH2POS Clock delay
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pcmTX2Channel16 pcmTX = 8 << 0 // CH2WID (Arbitrary width between 8 and 16 is supported)
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)
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type pcmDreq uint32
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// Page 134-135
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const (
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// 31 reserved
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pcmDreqTXPanicShift = 24
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pcmDreqTXPanicMask pcmDreq = 0x7F << pcmDreqTXPanicShift // TX_PANIC Panic level
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// 23 reserved
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pcmDreqRXPanicShift = 16
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pcmDreqRXPanicMask pcmDreq = 0x7F << pcmDreqRXPanicShift // RX_PANIC Panic level
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// 15 reserved
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pcmDreqTXLevelShift = 8
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pcmDreqTXLevelMask pcmDreq = 0x7F << pcmDreqTXPanicShift // TX Request Level
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// 7 reserved
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pcmDreqRXLevelShift = 0
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pcmDreqRXLevelMask pcmDreq = 0x7F << pcmDreqRXPanicShift // RX Request Level
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)
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type pcmInterrupt uint32
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// Page 135
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const (
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// 31:4 reserved
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pcmIntRXErr pcmInterrupt = 1 << 3 // RXERR RX error interrupt enable
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pcmIntTXErr pcmInterrupt = 1 << 2 // TXERR TX error interrupt enable
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pcmIntRXEnable pcmInterrupt = 1 << 1 // RXR RX Read interrupt enable
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pcmIntTXEnable pcmInterrupt = 1 << 0 // TXW TX Write interrupt enable
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)
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type pcmIntStatus uint32
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// Page 135-136
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const (
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// 31:4 reserved
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pcmIntStatRXErr pcmIntStatus = 1 << 3 // RXERR RX error occurred / clear
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pcmIntStatTXErr pcmIntStatus = 1 << 2 // TXERR TX error occurred / clear
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pcmIntStatRXEnable pcmIntStatus = 1 << 1 // RXR RX Read interrupt occurred / clear
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pcmIntStatTXEnable pcmIntStatus = 1 << 0 // TXW TX Write interrupt occurred / clear
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pcmIntStatusClear pcmIntStatus = 0xF
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)
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// pcmGray puts it into a special data/strobe mode that is under 'best effort'
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// contract.
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type pcmGray uint32
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// Page 136-137
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const (
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// 31:22 reserved
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pcmGrayRXFIFOLevelShift = 16
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pcmGrayRXFIFOLevelMask pcmGray = 0x3F << pcmGrayRXFIFOLevelShift // RXFIFOLEVEL How many words in RXFIFO
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pcmGrayFlushShift = 10
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pcmGrayFlushMask = 0x3F << pcmGrayFlushShift // FLUSHED How many bits were valid when flush occurred
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pcmGrayRXLevelShift = 4
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pcmGrayRXLevelMask pcmGray = 0x3F << pcmGrayRXLevelShift // RXLEVEL How many GRAY coded bits received
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pcmGrayFlush pcmGray = 1 << 2 // FLUSH
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pcmGrayClear pcmGray = 1 << 1 // CLR
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pcmGrayEnable pcmGray = 1 << 0 // EN
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)
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// Page 119
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type pcmMap struct {
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cs pcmCS // CS_A Control Status
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fifo uint32 // FIFO_A FIFO register
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mode pcmMode // MODE_A Operation mode
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rxc pcmRX // RXC_A RX control
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txc pcmTX // TXC_A TX control
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dreq pcmDreq // DREQ_A DMA control
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inten pcmInterrupt // INTEN_A Interrupt enable
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intstc pcmIntStatus // INTSTC_A Interrupt status
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gray pcmGray // GRAY Gray mode input processing
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}
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func (p *pcmMap) GoString() string {
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return fmt.Sprintf(
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"{\n cs: 0x%x,\n mode: 0x%x,\n rxc: 0x%x,\n txc: 0x%x,\n dreq: 0x%x,\n inten: 0x%x,\n intstc: 0x%x,\n gray: 0x%x,\n}",
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p.cs, p.mode, p.rxc, p.txc, p.dreq, p.inten, p.intstc, p.gray)
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}
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func (p *pcmMap) reset() {
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p.cs = 0
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// In theory need to wait the equivalent of 2 PCM clocks.
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// TODO(maruel): Use pcmSync busy loop to synchronize.
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Nanospin(time.Microsecond)
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// Hard reset
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p.fifo = 0
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p.mode = 0
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p.rxc = 0
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p.txc = 0
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p.dreq = 0
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p.inten = 0
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p.intstc = pcmIntStatusClear
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p.gray = 0
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// Clear pcmStandby / pcm
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}
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// set initializes 8 bits stream via DMA with no delay and no FS.
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func (p *pcmMap) set() {
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p.cs |= pcmEnable
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p.txc = pcmTX1Width | pcmTX1Channel16 | pcmTX1Enable // 32bit TX
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p.mode = (32 - 1) << pcmFrameLengthShift
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p.cs |= pcmTXClear | pcmRXClear
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// In theory need to wait the equivalent of 2 PCM clocks.
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// TODO(maruel): Use pcmSync busy loop to synchronize.
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Nanospin(time.Microsecond)
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p.dreq = 0x10<<pcmDreqTXPanicShift | 0x30<<pcmDreqTXLevelShift
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p.cs |= pcmDMAEnable
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// pcmTXThresholdOne ?
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p.cs |= pcmTXEnable
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}
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// setPCMClockSource sets the PCM clock.
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//
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// It may select an higher frequency than the one requested.
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//
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// Other potentially good clock sources are PWM, SPI and UART.
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func setPCMClockSource(f physic.Frequency) (physic.Frequency, uint32, error) {
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if drvDMA.pcmMemory == nil {
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return 0, 0, errors.New("subsystem PCM not initialized")
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}
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if drvDMA.clockMemory == nil {
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return 0, 0, errors.New("subsystem Clock not initialized")
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}
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actual, divs, err := drvDMA.clockMemory.pcm.set(f, 1)
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if err == nil {
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drvDMA.pcmMemory.cs = 0
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}
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// Convert divisor into wait cycles.
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return actual, divs, err
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}
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