475 lines
16 KiB
Go
475 lines
16 KiB
Go
// Copyright 2016 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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// Unlike the bcm283x, the allwinner CPUs do not have a "clear bit" and "set
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// bit" registers, they only have the data register. Also, allwinner CPUs do
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// not support linked lists of DMA buffers. On the other hand, the Allwinner DMA
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// controller supports 8 bits transfers instead of 32-128 bits that the bcm283x
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// DMA controller supports.
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//
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// This means that only 8 bits can be used per sample, and only one stream is
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// necessary. This results in 1/8th th memory usage than on the bcm283x. The
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// drawback is that a block of 8 contiguous GPIO pins must be dedicated to the
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// stream.
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package allwinner
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import (
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"errors"
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"fmt"
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"log"
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"os"
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"periph.io/x/periph"
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"periph.io/x/periph/host/pmem"
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)
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// dmaMap represents the DMA memory mapped CPU registers.
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//
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// This map is specific to the currently supported CPUs and will have to be
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// adapted as more CPUs are supported. In particular the number of physical
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// channels varies across different CPUs.
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//
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// Note that we modify the DMA controllers without telling the kernel driver.
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// The driver keeps its own table of which DMA channel is available so this
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// code could effectively crash the whole system. It practice this works.
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// #everythingisfine
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type dmaMap struct {
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irqEn dmaR8Irq // DMA_IRQ_EN_REG
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irqPendStas dmaR8PendingIrq // DMA_IRQ_PEND_STAS_REG
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reserved0 [(0x100 - 8) / 4]uint32 //
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normal [8]dmaR8NormalGroup // 0x100 The "8" "normal" DMA channels (only one active at a time so there's effectively one)
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reserved1 [0x100 / 4]uint32 //
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dedicated [8]dmaDedicatedGroup // 0x300 The 8 "dedicated" (as in actually existing) DMA channels
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}
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func (d *dmaMap) getDedicated() int {
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for i := len(d.dedicated) - 1; i >= 0; i-- {
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if d.dedicated[i].isAvailable() {
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return i
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}
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}
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return -1
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}
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// dmaNormalGroup is the control registers for the first block of 8 DMA
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// controllers.
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//
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// They can be intentionally slowed down, unlike the dedicated DMA ones.
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//
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// The big caveat is that only one controller can be active at a time and the
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// execution sequence is in accordance with the priority level. This means that
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// two normal DMA cannot be used to do simultaneous read and write. This
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// feature is critical for bus bitbanging.
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type dmaR8NormalGroup struct {
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cfg ndmaR8Cfg // NDMA_CTRL_REG
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srcAddr uint32 // NDMA_SRC_ADDR_REG
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dstAddr uint32 // NDMA_DEST_ADDR_REG
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byteCounter uint32 // NDMA_BC_REG
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reserved [4]uint32 //
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}
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func (d *dmaR8NormalGroup) isAvailable() bool {
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return d.cfg == 0 && d.srcAddr == 0 && d.dstAddr == 0 && d.byteCounter == 0
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}
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func (d *dmaR8NormalGroup) release() error {
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d.srcAddr = 0
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d.dstAddr = 0
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d.byteCounter = 0
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d.cfg = ndmaLoad
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//drvDMA.dmaMemory.irqEn &^= ...
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//drvDMA.dmaMemory.irqPendStas &^= ...
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return nil
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}
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// dmaNormalGroup is the control registers for the second block of 8 DMA
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// controllers.
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//
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// They support different DReq and can do non-linear streaming.
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type dmaDedicatedGroup struct {
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cfg ddmaR8Cfg // DDMA_CTRL_REG
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srcAddr uint32 // DDMA_SRC_ADDR_REG
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dstAddr uint32 // DDMA_DEST_ADDR_REG
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byteCounter uint32 // DDMA_BC_REG (24 bits)
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reserved0 [2]uint32 //
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param ddmaR8Param // DDMA_PARA_REG (dedicated DMA only)
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reserved1 uint32 //
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}
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func (d *dmaDedicatedGroup) isAvailable() bool {
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return d.cfg == 0 && d.srcAddr == 0 && d.dstAddr == 0 && d.byteCounter == 0 && d.param == 0
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}
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func (d *dmaDedicatedGroup) set(srcAddr, dstAddr, l uint32, srcIO, dstIO bool, src ddmaR8Cfg) {
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d.srcAddr = srcAddr
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d.dstAddr = dstAddr
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d.byteCounter = l
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// TODO(maruel): Slow down the clock by another 2*250x
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//d.param = ddmaR8Param(250 | 250<<16)
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d.param = ddmaR8Param(1<<24 | 1<<8 | 1)
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// All these have value 0. This statement only exist for documentation.
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cfg := ddmaDstWidth8 | ddmaDstBurst1 | ddmaDstLinear | ddmaSrcWidth8 | ddmaSrcLinear | ddmaSrcBurst1
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cfg |= src | ddmaBCRemain
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if srcIO {
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cfg |= ddmaSrcIOMode
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} else if dstIO {
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cfg |= ddmaDstIOMode
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}
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d.cfg = ddmaLoad | cfg
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for i := 0; d.cfg&ddmaLoad != 0 && i < 100000; i++ {
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}
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if d.cfg&ddmaLoad != 0 {
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log.Printf("failed to load DDMA: %# v\n", d)
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}
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}
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func (d *dmaDedicatedGroup) release() error {
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d.param = 0
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d.srcAddr = 0
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d.dstAddr = 0
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d.byteCounter = 0
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d.cfg = ddmaLoad
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//drvDMA.dmaMemory.irqEn &^= ...
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//drvDMA.dmaMemory.irqPendStas &^= ...
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return nil
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}
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const (
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// 31 reserved
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dma7QueueEndIrq dmaA64Irq = 1 << 30 // DMA7_END_IRQ_EN; DMA 7 Queue End Transfer Interrupt Enable.
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dma7PackageEndIrq dmaA64Irq = 1 << 29 // DMA7_PKG_IRQ_EN; DMA 7 Package End Transfer Interrupt Enable.
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dma7HalfIrq dmaA64Irq = 1 << 28 // DMA7_HLAF_IRQ_EN; DMA 7 Half Package Transfer Interrupt Enable.
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// ...
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// 3 reserved
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dma0QueueEndIrq dmaA64Irq = 1 << 2 // DMA0_END_IRQ_EN; DMA 0 Queue End Transfer Interrupt Enable.
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dma0PackageEndIrq dmaA64Irq = 1 << 1 // DMA0_PKG_IRQ_EN; DMA 0 Package End Transfer Interrupt Enable.
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dma0HalfIrq dmaA64Irq = 1 << 0 // DMA0_HLAF_IRQ_EN; DMA 0 Half Package Transfer Interrupt Enable.
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)
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// DMA_IRQ_EN_REG
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// A64: Page 199-201.
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type dmaA64Irq uint32
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const (
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ddma7EndIrq dmaR8Irq = 1 << 31 // DDMA7_END_IRQ_EN
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ddma7HalfIreq dmaR8Irq = 1 << 30 // DDMA7_HF_IRQ_EN
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// ...
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ddma0EndIrq dmaR8Irq = 1 << 17 // DDMA0_END_IRQ_EN
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ddma0HalfIreq dmaR8Irq = 1 << 16 // DDMA0_HF_IRQ_EN
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ndma7EndIrq dmaR8Irq = 1 << 15 // NDMA7_END_IRQ_EN
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ndma7HalfIreq dmaR8Irq = 1 << 16 // NDDMA7_HF_IRQ_EN
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// ...
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ndma0EndIrq dmaR8Irq = 1 << 1 // NDMA0_END_IRQ_EN
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ndma0HFIreq dmaR8Irq = 1 << 0 // NDMA0_HF_IRQ_EN
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)
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// DMA_IRQ_EN_REG
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// R8: Page 124-126.
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type dmaR8Irq uint32
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const (
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// 31 reserved
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dma7QueueEndIrqPend dmaA64PendingIrq = 1 << 30 // DMA7_QUEUE_IRQ_PEND; DMA 7 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
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dma7PackageEndIrqPend dmaA64PendingIrq = 1 << 29 // DMA7_PKG_IRQ_PEND; DMA 7 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
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dma7HalfIrqPend dmaA64PendingIrq = 1 << 28 // DMA7_HLAF_IRQ_PEND; DMA 7 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
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// ...
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// 3 reserved
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dma0QueueEndIrqPend dmaA64PendingIrq = 1 << 2 // DMA0_QUEUE_IRQ_PEND; DMA 0 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
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dma0PackageEndIrqPend dmaA64PendingIrq = 1 << 1 // DMA0_PKG_IRQ_PEND; DMA 0 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
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dma0HalfIrqPend dmaA64PendingIrq = 1 << 0 // DMA0_HLAF_IRQ_PEND; DMA 0 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it.
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)
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// DMA_IRQ_PEND_REG0
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// A64: Page 201-203.
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type dmaA64PendingIrq uint32
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const (
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ddma7EndIrqPend dmaR8PendingIrq = 1 << 31 // DDMA7_END_IRQ_PEND
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ddma7HalfIreqPend dmaR8PendingIrq = 1 << 30 // DDMA7_HF_IRQ_PEND
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// ...
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ddma0EndIrqPend dmaR8PendingIrq = 1 << 17 // DDMA0_END_IRQ_PEND
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ddma0HalfIreqPend dmaR8PendingIrq = 1 << 16 // DDMA0_HF_IRQ_PEND
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ndma7EndIrqPend dmaR8PendingIrq = 1 << 15 // NDMA7_END_IRQ_PEND
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ndma7HalfIreqPend dmaR8PendingIrq = 1 << 16 // NDDMA7_HF_IRQ_PEND
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// ...
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ndma0EndIrqPend dmaR8PendingIrq = 1 << 1 // NDMA0_END_IRQ_PEND
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ndma0HalfIreqPend dmaR8PendingIrq = 1 << 0 // NDMA0_HF_IRQ_PEND
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)
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// DMA_IRQ_PEND_STAS_REG
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// R8: Page 126-129.
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type dmaR8PendingIrq uint32
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const (
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ndmaLoad ndmaR8Cfg = 1 << 31 // NDMA_LOAD
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ndmaContinuous ndmaR8Cfg = 1 << 30 // NDMA_CONTI_EN Continuous mode
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ndmaWaitClk0 ndmaR8Cfg = 0 << 27 // NDMA_WAIT_STATE Number of clock to wait for
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ndmaWaitClk2 ndmaR8Cfg = 1 << 27 // 2(n+1)
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ndmaWaitClk6 ndmaR8Cfg = 2 << 27 //
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ndmaWaitClk8 ndmaR8Cfg = 3 << 27 //
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ndmaWaitClk10 ndmaR8Cfg = 4 << 27 //
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ndmaWaitClk12 ndmaR8Cfg = 5 << 27 //
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ndmaWaitClk14 ndmaR8Cfg = 6 << 27 //
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ndmaWaitClk16 ndmaR8Cfg = 7 << 27 //
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ndmaDstWidth32 ndmaR8Cfg = 2 << 25 // NDMA_DST_DATA_WIDTH
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ndmaDstWidth16 ndmaR8Cfg = 1 << 25 //
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ndmaDstWidth8 ndmaR8Cfg = 0 << 25 //
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ndmaDstBurst8 ndmaR8Cfg = 2 << 23 // NDMA_DST_BST_LEN
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ndmaDstBurst4 ndmaR8Cfg = 1 << 23 //
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ndmaDstBurst1 ndmaR8Cfg = 0 << 23 //
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// 22 reserved NDMA_CFG_DST_NON_SECURE ?
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ndmaDstAddrNoInc ndmaR8Cfg = 1 << 21 // NDMA_DST_ADDR_TYPE
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ndmaDstDrqIRTX ndmaR8Cfg = 0 << 16 // NDMA_DST_DRQ_TYPE
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ndmaDstDrqUART1TX ndmaR8Cfg = 9 << 16 //
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ndmaDstDrqUART3TX ndmaR8Cfg = 11 << 16 //
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ndmaDstDrqAudio ndmaR8Cfg = 19 << 16 // 24.576MHz (Page 53)
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ndmaDstDrqSRAM ndmaR8Cfg = 21 << 16 //
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ndmaDstDrqSPI0TX ndmaR8Cfg = 24 << 16 //
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ndmaDstDrqSPI1TX ndmaR8Cfg = 25 << 16 //
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ndmaDstDrqSPI2TX ndmaR8Cfg = 26 << 16 //
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ndmaDstDrqUSB1 ndmaR8Cfg = 27 << 16 // 480MHz
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ndmaDstDrqUSB2 ndmaR8Cfg = 28 << 16 //
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ndmaDstDrqUSB3 ndmaR8Cfg = 29 << 16 //
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ndmaDstDrqUSB4 ndmaR8Cfg = 30 << 16 //
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ndmaDstDrqUSB5 ndmaR8Cfg = 31 << 16 //
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ndmaBCRemain ndmaR8Cfg = 1 << 15 // BC_MODE_SEL
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// 14:11 reserved
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ndmaSrcWidth32 ndmaR8Cfg = 2 << 9 // NDMA_SRC_DATA_WIDTH
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ndmaSrcWidth16 ndmaR8Cfg = 1 << 9 //
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ndmaSrcWidth8 ndmaR8Cfg = 0 << 9 //
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ndmaSrcBurst8 ndmaR8Cfg = 2 << 7 // NDMA_SRC_BST_LEN
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ndmaSrcBurst4 ndmaR8Cfg = 1 << 7 //
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ndmaSrcBurst1 ndmaR8Cfg = 0 << 7 //
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// 6 reserved NDMA_CFG_SRC_NON_SECURE ?
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ndmaSrcAddrNoInc ndmaR8Cfg = 1 << 5 // NDMA_SRC_ADDR_TYPE
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ndmaSrcDrqIRTX ndmaR8Cfg = 0 << 0 // NDMA_SRC_DRQ_TYPE
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ndmaSrcDrqUART1RX ndmaR8Cfg = 9 << 0 //
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ndmaSrcDrqUART3RX ndmaR8Cfg = 11 << 0 //
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ndmaSrcDrqAudio ndmaR8Cfg = 19 << 0 // 24.576MHz (Page 53)
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ndmaSrcDrqSRAM ndmaR8Cfg = 21 << 0 //
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ndmaSrcDrqSDRAM ndmaR8Cfg = 22 << 0 // 0~400MHz
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ndmaSrcDrqTPAD ndmaR8Cfg = 23 << 0 //
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ndmaSrcDrqSPI0RX ndmaR8Cfg = 24 << 0 //
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ndmaSrcDrqSPI1RX ndmaR8Cfg = 25 << 0 //
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ndmaSrcDrqSPI2RX ndmaR8Cfg = 26 << 0 //
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ndmaSrcDrqUSB1 ndmaR8Cfg = 27 << 0 // 480MHz
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ndmaSrcDrqUSB2 ndmaR8Cfg = 28 << 0 //
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ndmaSrcDrqUSB3 ndmaR8Cfg = 29 << 0 //
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ndmaSrcDrqUSB4 ndmaR8Cfg = 30 << 0 //
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ndmaSrcDrqUSB5 ndmaR8Cfg = 31 << 0 //
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)
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// NDMA_CTRL_REG
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// R8: Page 129-131.
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type ndmaR8Cfg uint32
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const (
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ddmaLoad ddmaR8Cfg = 1 << 31 // DDMA_LOAD
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ddmaBusy ddmaR8Cfg = 1 << 30 // DDMA_BSY_STA
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ddmaContinuous ddmaR8Cfg = 1 << 29 // DDMA_CONTI_MODE_EN
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// 28:27 reserved 28 = DDMA_CFG_DST_NON_SECURE ?
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ddmaDstWidth32 ddmaR8Cfg = 2 << 25 // DDMA_DST_DATA_WIDTH
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ddmaDstWidth16 ddmaR8Cfg = 1 << 25 //
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ddmaDstWidth8 ddmaR8Cfg = 0 << 25 //
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ddmaDstBurst8 ddmaR8Cfg = 2 << 23 // DDMA_DST_BST_LEN
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ddmaDstBurst4 ddmaR8Cfg = 1 << 23 //
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ddmaDstBurst1 ddmaR8Cfg = 0 << 23 //
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ddmaDstVertical ddmaR8Cfg = 3 << 21 // DDMA_ADDR_MODE; no idea what it's use it. It's not explained in the datasheet ...
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ddmaDstHorizontal ddmaR8Cfg = 2 << 21 // ... and the official drivers/dma/sun6i-dma.c driver doesn't use it
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ddmaDstIOMode ddmaR8Cfg = 1 << 21 // Non incrementing
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ddmaDstLinear ddmaR8Cfg = 0 << 21 // Normal incrementing position
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ddmaDstDrqSRAM ddmaR8Cfg = 0 << 16 // DDMA_DST_DRQ_SEL
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ddmaDstDrqSDRAM ddmaR8Cfg = 1 << 16 // DDR ram speed
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ddmaDstDrqNAND ddmaR8Cfg = 3 << 16 //
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ddmaDstDrqUSB0 ddmaR8Cfg = 4 << 16 //
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ddmaDstDrqSPI1TX ddmaR8Cfg = 8 << 16 //
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ddmaDstDrqCryptoTX ddmaR8Cfg = 10 << 16 //
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ddmaDstDrqTCON0 ddmaR8Cfg = 14 << 16 //
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ddmaDstDrqSPI0TX ddmaR8Cfg = 26 << 16 //
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ddmaDstDrqSPI2TX ddmaR8Cfg = 28 << 16 //
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ddmaBCRemain ddmaR8Cfg = 1 << 15 // BC_MODE_SEL
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// 14:11 reserved
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ddmaSrcWidth32 ddmaR8Cfg = 2 << 9 // DDMA_SRC_DATA_WIDTH
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ddmaSrcWidth16 ddmaR8Cfg = 1 << 9 //
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ddmaSrcWidth8 ddmaR8Cfg = 0 << 9 //
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ddmaSrcBurst8 ddmaR8Cfg = 2 << 7 // DDMA_SRC_BST_LEN
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ddmaSrcBurst4 ddmaR8Cfg = 1 << 7 //
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ddmaSrcBurst1 ddmaR8Cfg = 0 << 7 //
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ddmaSrcVertical ddmaR8Cfg = 3 << 5 // DDMA_SRC_ADDR_MODE
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ddmaSrcHorizontal ddmaR8Cfg = 2 << 5 //
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ddmaSrcIOMode ddmaR8Cfg = 1 << 5 // Non incrementing
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ddmaSrcLinear ddmaR8Cfg = 0 << 5 // Normal incrementing position
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// 4:0 drq
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ddmaSrcDrqSRAM ddmaR8Cfg = 0 << 0 // DDMA_SRC_DRQ_TYPE
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ddmaSrcDrqSDRAM ddmaR8Cfg = 1 << 0 //
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ddmaSrcDrqNAND ddmaR8Cfg = 3 << 0 //
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ddmaSrcDrqUSB0 ddmaR8Cfg = 4 << 0 //
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ddmaSrcDrqSPI1RX ddmaR8Cfg = 9 << 0 //
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ddmaSrcDrqCryptoRX ddmaR8Cfg = 11 << 0 //
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ddmaSrcDrqSPI0RX ddmaR8Cfg = 27 << 0 //
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ddmaSrcDrqSPI2RX ddmaR8Cfg = 29 << 0 //
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)
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// DDMA_CFG_REG
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// R8: Page 131-134.
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type ddmaR8Cfg uint32
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const (
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// For each value, N+1 is actually used.
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ddmaDstBlkSizeMask ddmaR8Param = 0xFF << 24 // DEST_DATA_BLK_SIZE
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ddmaDstWaitClkCycleMask ddmaR8Param = 0xFF << 16 // DEST_WAIT_CLK_CYC
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ddmaSrcBlkSizeMask ddmaR8Param = 0xFF << 8 // SRC_DATA_BLK_SIZE
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ddmaSrcWaitClkCycleMask ddmaR8Param = 0xFF << 0 // SRC_WAIT_CLK_CYC
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)
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// DDMA_PARA_REG
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// R8: Page 134.
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type ddmaR8Param uint32
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// smokeTest allocates two physical pages, ask the DMA controller to copy the
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// data from one page to another (with a small offset) and make sure the
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// content is as expected.
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//
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// This should take a fraction of a second and will make sure the driver is
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// usable.
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func smokeTest() error {
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const size = 4096 // 4kb
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const holeSize = 1 // Minimum DMA alignment.
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alloc := func(s int) (pmem.Mem, error) {
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return pmem.Alloc(s)
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}
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copyMem := func(pDst, pSrc uint64) error {
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n := drvDMA.dmaMemory.getDedicated()
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if n == -1 {
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return errors.New("no channel available")
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}
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drvDMA.dmaMemory.irqEn &^= 3 << uint(2*n+16)
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drvDMA.dmaMemory.irqPendStas = 3 << uint(2*n+16)
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ch := &drvDMA.dmaMemory.dedicated[n]
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defer func() {
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_ = ch.release()
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}()
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ch.set(uint32(pSrc), uint32(pDst)+holeSize, 4096-2*holeSize, false, false, ddmaDstDrqSDRAM|ddmaSrcDrqSDRAM)
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for ch.cfg&ddmaBusy != 0 {
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}
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return nil
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}
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return pmem.TestCopy(size, holeSize, alloc, copyMem)
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}
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// driverDMA implements periph.Driver.
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//
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// It implements much more than the DMA controller, it also exposes the clocks,
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// the PWM and PCM controllers.
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type driverDMA struct {
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// dmaMemory is the memory map of the CPU DMA registers.
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dmaMemory *dmaMap
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// pwmMemory is the memory map of the CPU PWM registers.
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pwmMemory *pwmMap
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// spiMemory is the memory mapping for the spi CPU registers.
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spiMemory *spiMap
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// clockMemory is the memory mapping for the clock CPU registers.
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clockMemory *clockMap
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// timerMemory is the memory mapping for the timer CPU registers.
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timerMemory *timerMap
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}
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func (d *driverDMA) String() string {
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return "allwinner-dma"
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}
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func (d *driverDMA) Prerequisites() []string {
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return []string{"allwinner-gpio"}
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}
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func (d *driverDMA) After() []string {
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return nil
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}
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func (d *driverDMA) Init() (bool, error) {
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// dmaBaseAddr is the physical base address of the DMA registers.
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var dmaBaseAddr uint32
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// pwmBaseAddr is the physical base address of the PWM registers.
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var pwmBaseAddr uint32
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// spiBaseAddr is the physical base address of the clock registers.
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var spiBaseAddr uint32
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// clockBaseAddr is the physical base address of the clock registers.
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var clockBaseAddr uint32
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// timerBaseAddr is the physical base address of the timer registers.
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var timerBaseAddr uint32
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if IsA64() {
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// Page 198.
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dmaBaseAddr = 0x1C02000
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// Page 194.
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pwmBaseAddr = 0x1C21400
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// Page 161.
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timerBaseAddr = 0x1C20C00
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// Page 81.
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clockBaseAddr = 0x1C20000
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// Page Page 545.
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spiBaseAddr = 0x01C68000
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} else if IsR8() {
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// Page 124.
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dmaBaseAddr = 0x1C02000
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// Page 83.
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pwmBaseAddr = 0x1C20C00 + 0x200
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// Page 85.
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timerBaseAddr = 0x1C20C00
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// Page 57.
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clockBaseAddr = 0x1C20000
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// Page 151.
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spiBaseAddr = 0x01C05000
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} else {
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// H3
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// Page 194.
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//dmaBaseAddr = 0x1C02000
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// Page 187.
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//pwmBaseAddr = 0x1C21400
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// Page 154.
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//timerBaseAddr = 0x1C20C00
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return false, errors.New("unsupported CPU architecture")
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|
}
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|
|
|
if err := pmem.MapAsPOD(uint64(dmaBaseAddr), &d.dmaMemory); err != nil {
|
|
if os.IsPermission(err) {
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|
return true, fmt.Errorf("need more access, try as root: %v", err)
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}
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|
return true, err
|
|
}
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|
|
|
if err := pmem.MapAsPOD(uint64(pwmBaseAddr), &d.pwmMemory); err != nil {
|
|
return true, err
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|
}
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|
if err := pmem.MapAsPOD(uint64(timerBaseAddr), &d.timerMemory); err != nil {
|
|
return true, err
|
|
}
|
|
if err := pmem.MapAsPOD(uint64(clockBaseAddr), &d.clockMemory); err != nil {
|
|
return true, err
|
|
}
|
|
if err := pmem.MapAsPOD(uint64(spiBaseAddr), &d.spiMemory); err != nil {
|
|
return true, err
|
|
}
|
|
|
|
return true, smokeTest()
|
|
}
|
|
|
|
func (d *driverDMA) Close() error {
|
|
// Stop DMA and PWM controllers.
|
|
return nil
|
|
}
|
|
|
|
func init() {
|
|
if false && isArm {
|
|
// TODO(maruel): This is intense, wait to be sure it works.
|
|
periph.MustRegister(&drvDMA)
|
|
}
|
|
}
|
|
|
|
var drvDMA driverDMA
|